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In `F33f`_`[computing`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Computing]`_`f, an `!inter-processor interrupt`! (`!IPI`!), also known as a `*shoulder tap`*, is a special type of `F33f`_`[interrupt`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Interrupt]`_`f by which one `F33f`_`[processor`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Processor_(computing)]`_`f may interrupt another processor in a `F33f`_`[multiprocessor`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Multiprocessor]`_`f system if the interrupting processor requires action from the other processor. Actions that might be requested include:

• Flush `F33f`_`[memory management unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Memory_management_unit]`_`f caches, such as `F33f`_`[translation lookaside buffers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Translation_lookaside_buffer]`_`f, on other processors when memory mappings are changed by one processor;

• Stop when the system is being shut down by one processor.

• Notify an alternate CPU of a malfunction for Alternate CPU Recovery (ACR).

• Notify a processor that higher-priority work is available.

• Notify a processor of work that cannot be done on all processors due to, e.g.,

• asymmetric access to `F33f`_`[I/O channels`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=I/O_channel]`_`f`:cite-ref-1[`F5bf`_`[1`#cite-note-1]`_`f]

• special features on some processors`:cite-ref-2[`F5bf`_`[2`#cite-note-2]`_`f]

>>Contents

• `F0af`_`[Mechanism`#mechanism]`_`f

• `F0af`_`[Examples`#examples]`_`f

• `F0af`_`[See also`#see-also]`_`f

• `F0af`_`[References`#references]`_`f

• `F0af`_`[External links`#external-links]`_`f

-─

>>Mechanism

The `F33f`_`[M65MP`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=OS/360_and_successors]`_`f option of `F33f`_`[OS/360`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=OS/360_and_successors]`_`f used the Direct Control feature of the `F33f`_`[S/360`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM_System/360]`_`f to generate an interrupt on another processor; on `F33f`_`[S/370`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM_System/370]`_`f and its successors, including `F33f`_`[z/Architecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Z/Architecture]`_`f, the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.

On `F33f`_`[IBM PC compatible`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM_PC_compatible]`_`f computers that use the `F33f`_`[Advanced Programmable Interrupt Controller`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Advanced_Programmable_Interrupt_Controller]`_`f (APIC), IPI signaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the `F33f`_`[interrupt vector`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Interrupt_vector]`_`f and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which then issues a corresponding interrupt to its own CPU.

>>Examples

In a multiprocessor system running `F33f`_`[Microsoft Windows`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Microsoft_Windows]`_`f, a processor may interrupt another processor for the following reasons, in addition to the ones listed above:`:cite-ref-3[`F5bf`_`[3`#cite-note-3]`_`f]

1. queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution;

2. kernel debugger breakpoint.

IPIs are given an `F33f`_`[IRQL`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IRQL_(Windows)]`_`f of 29.`:cite-ref-4[`F5bf`_`[4`#cite-note-4]`_`f]

>>See also

• `F33f`_`[Interrupt`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Interrupt]`_`f

• `F33f`_`[Interrupt handler`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Interrupt_handler]`_`f

• `F33f`_`[Non-maskable interrupt`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Non-maskable_interrupt]`_`f (NMI)

>>References

`:cite-note-1`!1.`! `F0af`_`[↑`#cite-ref-1]`_`f "Appendix F: Multiprocessing Extensions" (PDF). `*OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505`* (PDF). Program Logic. `F33f`_`[IBM`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM]`_`f. p. 271. GY28-6616-9. Retrieved August 28, 2022.

`:cite-note-2`!2.`! `F0af`_`[↑`#cite-ref-2]`_`f "AMD Technical Information Portal". `*docs.amd.com`*. Retrieved 2024-07-18.

`:cite-note-3`!3.`! `F0af`_`[↑`#cite-ref-3]`_`f "Inter Processor Interrupt usage". `*Stack Overflow`*. Retrieved 2024-07-18.

`:cite-note-4`!4.`! `F0af`_`[↑`#cite-ref-4]`_`f `:citerefmatt2002`aMatt (2002-04-28). "Understanding IRQL". Archived from the original on 2019-10-14. Retrieved 2014-12-06.

>>External links

• Interrupts and Exceptions

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